posted                   

code:

---

 ==============================Standard==================================
	mov eax, 8000C290h  		; DRAM Configuration Low Address
	mov dx,0CF8h			; set port address
	out dx,eax			; send address through the port
	mov dx,0CFCh			; set port data
	in eax,dx			; fetch data
	and eax, 0F1FFFFFFh 		; Bypass Max
	or  eax, 00E000000h 	 	; 7x
	out dx, eax			; send new data

	mov eax, 8000C290h  		; DRAM Configuration Low Address
	mov dx,0CF8h			; set port address
	out dx,eax			; send address through the port
	mov dx,0CFCh			; set port data
	in eax,dx			; fetch data
	and eax, 0FFFF3FFFh 		; Read/Write Queue Bypass
	or eax,  00000C000h     	; 16x
	out dx, eax			; send new data 

---

code:

---

============================Combined====================================
 	mov eax, 8000C290h  		; DRAM Configuration Low Address
	mov dx,0CF8h			; set port address
	out dx,eax			; send address through the port
	mov dx,0CFCh			; set port data
	in eax,dx			; fetch data
	and eax, 0F1FFFFFFh 		; Bypass Max
	or  eax, 00E000000h 	 	; 7x
	and eax, 0FFFF3FFFh 		; Read/Write Queue Bypass
	or eax,  00000C000h     	; 16x
	out dx, eax			; send new data 

---

code:

---

 =============================DWord======================================
	mov eax, 8000C290h  		; DRAM Configuration Low Address
	mov dx,0CF8h			; set port address
	out dx,eax			; send address through the port
	mov dx,0CFCh			; set port data
	in eax,dx			; fetch data
	and eax, 0F1FF3FFFh 		; Bypass Max & R/W Queue Bypass
	or  eax, 00E00C000h 	 	; 7x & 16x
	out dx, eax			; send new data

 

---

code:

---

============================21 Timings====================================
 	mov eax,08000C288h		; DRAM Timing Low address
	mov ebx,000EDC224h		; register data for: Cas, Trcd, Trp, Tras,
					; Trc, Trrd, Twr
	mov dx,0CF8h			; set port address
	out dx,eax			; send address through the port
	mov dx,0CFCh			; set port data
	in eax,dx			; fetch data
	and eax,0FF000CC8h		; set data byte to zero 
	or eax,ebx			; increase data by new setting
	out dx,eax			; send data through port data

	mov eax,08000C28Ch		; cDRAM Timing High address
	mov ebx,06DB20300h		; register data for: Twtr, Tref, Trfc 
	mov dx,0CF8h			; set port address
	out dx,eax			; send address through the port
	mov dx,0CFCh			; set port data
	in eax,dx			; fetch data
	and eax,0000CFCFFh		; set data byte to zero 
	or eax,ebx			; increase data by new setting
	out dx,eax			; send data through port data

	mov eax,08000C290h		; DRAM Configuration Low address
	mov ebx,000000080h		; register data for: Drive Strength Normal
	mov dx,0CF8h			; set port address
	out dx,eax			; send address through the port
	mov dx,0CFCh			; set port data
	in eax,dx			; fetch data
	and eax,0FFFFFF7Fh		; set data byte to zero 
	or eax,ebx			; increase data by new setting
	out dx,eax			; send data through port data

	mov eax,08000C294h		; DRAM Configuration High address
	mov ebx,00F100090h		; register data for: Async, CRC, QBypass
	mov dx,0CF8h			; set port address
	out dx,eax			; send address through the port
	mov dx,0CFCh			; set port data
	in eax,dx			; fetch data
	and eax,0F0EFFF0Fh		; set data byte to zero 
	or eax,ebx			; increase data by new setting
	out dx,eax			; send data through port data

	mov eax,08000C2A0h		; DRAM Miscellaneous address
	mov ebx,00000012Ch		; register data for: Idle Cycle, 
					; Dynamic Idle, Queue Bypass, Trfc0-3
	mov dx,0CF8h			; set port address
	out dx,eax			; send address through the port
	mov dx,0CFCh			; set port data
	in eax,dx			; fetch data
	and eax,0FFFFFE13h		; set data byte to zero 
	or eax,ebx			; increase data by new setting 

---

code:

---

 ASL:
;========================== Setup DRAM Config High Address =======================
	mov ebx, 0h		;clear
	mov ecx, 0h		;clear
;=============================== Async Latency ===================================
	mov eax, 0h		;clear
	mov al, 21h		;set index-21h
	out 72h, al		;send index thru port
	in al, 73h		;fetch data
	and al, 0Fh		;mask 0000.1111
	mov cl, al		;save for later

	mov eax,08000C294h	;DRAM Config High Address
	mov dx,0CF8h		;set port address
	out dx,eax		;send address thru port
	mov dx,0CFCh		;set port data
	in eax,dx		;fetch dword at DRAM Config High Address

	mov ebx, eax		;save dword in case no change
	cmp cl, 00h		;see if AUTO was selected
	je NEXT			;jump, AUTO selected

	mov eax, 0		;clear
	mov al, cl		;move index to eax
;mask 0Fh
	add eax, 04h		;add 04h to eax - 0000.0001+0000.0100 = 0000.0101
	sal eax, 04h		;shift left 4 bits - 0101.0000<----0000.0101
;mask F0h
	;add eax, 40h		;add 40h to eax 0001.0000+0100.0000 = 0101.0000
	;sal eax, 04h		;shift left 4 bits - not needed
;============================== READ-MODIFY-WRITE ================================

	and ebx,0FFFFFF0Fh	;Mask Async Latency Bit
	or eax,ebx		;add Async Latency bits to dword    
	out dx,eax		;Send dword at DRAM Config High Address


; Auto, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 0Bh settings 0Fh mask 

---

Edit: As I get more up to speed in Assembly, I'm noticing things I should not have done. The one for this topic is to use the directive "shr" instead of "sar" when shifting right. "sar" keeps the left-most bit as it could be a sign bit.

--------------------
Too Many Computers,... Too Little Time ..... Com'on ???..!

posted                   

quote:

---

This new patch only initializes one register at a time and gives enough "CPU clock-cycle" to the PCI bus intensive routine. Personally, I think that to appropriately initialize a PCI chipset it's not enough just by relaxing the read-write timing, but more importantly we have to initialize only one register at a time in order to minimize the "sudden-load" in the chipset. This is especially true for performance-related registers within the chipset. In my tests for this new patch, I placed the call to the patch in a few places within the POST-jump-table an everyone of them work flawlessly as expected. The testing has been carried out more than 100 boot-reboot cycle for each variant

---

posted                   

code:

---

 	mov eax,08000C288h		; DRAM Timing Low address
	mov ebx,000200000h		; copy register data for Twr: 5T
	mov dx,0CF8h			; set port address
	out dx,eax			; send address through the port
	mov dx,0CFCh			; set port data
	in eax,dx			; fetch data
	and eax,0FFCFFFFFh		; set data byte to zero 
	or eax,ebx			; increase data by new setting
	out dx,eax			; send data through port data

	mov eax,08000C288h		; DRAM Timing Low address
	mov ebx,000800000h		; copy register data for Trrd: 4T
	mov dx,0CF8h			; set port address
	out dx,eax			; send address through the port
	mov dx,0CFCh			; set port data
	in eax,dx			; fetch data
	and eax,0FF3FFFFFh		; set data byte to zero 
	or eax,ebx			; increase data by new setting
	out dx,eax			; send data through port data 

---

code:

---

 	mov eax,08000C288h		; DRAM Timing Low address
	mov ebx,000200000h		; copy register data for Twr: 5T
	mov dx,0CF8h			; set port address
	out dx,eax			; send address through the port
	mov dx,0CFCh			; set port data
	in eax,dx			; fetch data
	and eax,0FFCFFFFFh		; set data byte to zero 
	or eax,ebx			; increase data by new setting
	out dx,eax			; send data through port data

	;mov eax,08000C288h		; DRAM Timing Low address
	;mov ebx,000800000h		; copy register data for Trrd: 4T
	;mov dx,0CF8h			; set port address
	;out dx,eax			; send address through the port
	;mov dx,0CFCh			; set port data

	in eax,dx			; fetch data
	and eax,0FF3FFFFFh		; set data byte to zero 
	or eax,ebx			; increase data by new setting
	out dx,eax			; send data through port data 

---

--------------------
Too Many Computers,... Too Little Time ..... Com'on ???..!

posted                   

code:

---

jmp $+2

---

The main point is to "wait" for the PCI Bus (PCIe or Hypertransport for your particular case) to be ready before sending the data to initialize the chipset. More over, it's important to only set/reset the bit(s) that we know or experiment with and leaving the rest to their unaltered form as it can harm the stability of the system as well.

Anyway, back then I intended to experiment with assembly instructions that would "serialize" i.e., "flushes" the cache before executing any PCI register related activity in the code. Nonetheless, I haven't got the time until now, maybe you guys can experiment with it ;-).

One more thing that we must be aware that certain PCI register is "one time set" only, i.e. you can only initialize it once, you cannot reinitialize it later. In Intel chipset document, some registers are mentioned to be of that type. In a case like this, the only option we have is to patch the system BIOS, because Option ROM simply wouldn't affect the register.

A little off-topic. But, I want to inform that I've got AMD690G mobo right now and new experiments should come from me ;-). Looking forward experimenting with RAM related initialization.

That's all for now guys. Keep up the good work. I'll be joining soon

--------------------
-- Human knowledge belongs to the world --

posted                   

OK,

So in the following code, where would the jmp short $+2 instruction(s) be placed:

code:

---

 ==============================Standard==================================
	mov eax, 8000C290h  		; DRAM Configuration Low Address
	mov dx,0CF8h			; set port address
	out dx,eax			; send address through the port
	mov dx,0CFCh			; set port data
	in eax,dx			; fetch data
	and eax, 0F1FFFFFFh 		; Bypass Max
	or  eax, 00E000000h 	 	; 7x
	out dx, eax			; send new data

	mov eax, 8000C290h  		; DRAM Configuration Low Address
	mov dx,0CF8h			; set port address
	out dx,eax			; send address through the port
	mov dx,0CFCh			; set port data
	in eax,dx			; fetch data
	and eax, 0FFFF3FFFh 		; Read/Write Queue Bypass
	or eax,  00000C000h     	; 16x
	out dx, eax			; send new data  

---

--------------------
Too Many Computers,... Too Little Time ..... Com'on ???..!

posted                   

quote:

---

Perhaps your code should be more dependant on the already existing setup value, and your value on a byte level AND/OR-ed into it after reading out the previous value, instead of a 'clean' mov ?

---

I am reading the existing value and changing only the bits of interest. When a single value in the memory timing is changed, are you saying only write to that single register and not the whole 32bit register, which is made up of 8-4 bit registers?

As some "timings" straddle 2 registers, and those registers contain either some or all bits for other timings, I don't know how to not re-write those bits that are not of interest when they are in the registers of interest.

Again, from the very beginning, all code generated by tictac and Pinczakko has written to the 32 bits even if only 1 setting is changed....

--------------------
Too Many Computers,... Too Little Time ..... Com'on ???..!

posted                   

code:

---

;------------------------------ file: mem_optimize.asm -----------------------------------
use16

start:
        pushf
        cli


        mov  cx, 0x50           ;patch the ioq register of the chipset
        call Read_PCI_Bus0_Byte
        or   al, 0x80
        mov  cx, 0x50
        call Write_PCI_Bus0_Byte

        mov  cx, 0x64           ;DRAM Bank 0/1 Interleave = 4-way
        call Read_PCI_Bus0_Byte
        or   al, 2
        mov  cx, 0x64
        call Write_PCI_Bus0_Byte

        mov  cx, 0x65           ;DRAM Bank 2/3 Interleave = 4-way
        call Read_PCI_Bus0_Byte
        or   al, 2
        mov  cx, 0x65
        call Write_PCI_Bus0_Byte

        mov  cx, 0x66           ;DRAM Bank 4/5 Interleave = 4-way
        call Read_PCI_Bus0_Byte
        or   al, 2
        mov  cx, 0x66
        call Write_PCI_Bus0_Byte

        mov  cx, 0x67           ;DRAM Bank 6/7 Interleave = 4-way
        call Read_PCI_Bus0_Byte
        or   al, 2
        mov  cx, 0x67
        call Write_PCI_Bus0_Byte

        mov  cx, 0x68           ;Allow pages of different bank to be active simultanoeusly
        call Read_PCI_Bus0_Byte
        or   al, 0x44
        mov  cx, 0x68
        call Write_PCI_Bus0_Byte

        mov  cx, 0x69           ;Fast DRAM Precharge for Different Bank
        call Read_PCI_Bus0_Byte
        or   al, 0x8
        mov  cx, 0x69
        call Write_PCI_Bus0_Byte

        mov  cx, 0x6C           ;Activate Fast TLB lookup
        call Read_PCI_Bus0_Byte
        or   al, 0x8
        mov  cx, 0x6C
        call Write_PCI_Bus0_Byte


        popf

        clc              ;indicate that this POST routine successful
        retn             ;return near to the header of the rom file


;-- Read_PCI_Byte__ --
;in: cx = dev_func_offset_addr
;out: al = reg_value

Read_PCI_Bus0_Byte:
        mov   ax, 8000h
        shl   eax, 10h
        mov   ax, cx
        and   al, 0FCh
        mov   dx, 0CF8h
        out   dx, eax
  ;<-- you can put the "relaxing" jump here -->
        mov   dl, 0FCh ; '?'
        mov   al, cl
        and   al, 3
        add   dl, al
        in    al, dx
  ;<-- you can put the "relaxing" jump here -->
        retn


;-- Write_Bus0_Byte --
;in: cx = dev_func_offset addr
;al = reg_value to write

Write_PCI_Bus0_Byte:
        xchg  ax, cx
        shl   ecx, 10h
        xchg  ax, cx
        mov   ax, 8000h
        shl   eax, 10h
        mov   ax, cx
        and   al, 0FCh
        mov   dx, 0CF8h
        out   dx, eax
  ;<-- you can put the "relaxing" jump here -->
        add   dl, 4
        or    dl, cl
        mov   eax, ecx
        shr   eax, 10h
        out   dx, al
  ;<-- you can put the "relaxing" jump here -->
        retn
;------------------------------ file: mem_optimize.asm -----------------------------------

---

posted                   

code:

---

cli

---

code:

---

sti

---

after you're done with it. This is assuming you're still coding an expansion ROM. If you make a system BIOS patch, you have to look at the current system state from the code surrounding your patch

--------------------
-- Human knowledge belongs to the world --