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Hi Phil! Damn! I forgot to redraw the information field of the Hyper-Threading Technology label. This field is used both “Enhanced 3DNow!” and “HTT” depending on which processor is installed – 32bit or 64-bit :-) BTW, I didn’t use Intel’s ID flags for determining of SSE3 and HTT. In the CPUID Guide for AMD Athlon 64 and AMD Opteron Processors. Revision 2.13. Confidential.” I found appropriate bits. Download a new build 1020http://cbid.amdclub.ru/files/cbid73t.zip. Besides, this build can enable/disable a Probe State for the processor, but only on nForce IGP chipset. nForce2 has the same function but I couldn’t find appropriate bit in the NB.
-------------------- PhenomII550BE+@3.6GHz/TA780G M2+/2x1GB KVR DDR2-800/WD500GB/RaidMAX case 500W/WS2003SP2 http://cbid.at.tut.by Posts: 138 | From: Belarus, Western Europe | Registered: Apr 2004
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Probe State: The Probe state is entered when the Northbridge connects the AMD Athlon system bus to probe the processor (for example, to snoop the processor caches) when the processor is in the Halt or Stop Grant state. When in the Probe state, the processor responds to a probe cycle in the same manner as when it is in the Working state. When the probe has been serviced, the processor returns to the same state as when it entered the Probe state (Halt or Stop Grant state). When probe activity is completed the processor only returns to a low-power state after the Northbridge disconnects the AMD Athlon system bus again.
Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E – November 2001
-------------------- PhenomII550BE+@3.6GHz/TA780G M2+/2x1GB KVR DDR2-800/WD500GB/RaidMAX case 500W/WS2003SP2 http://cbid.at.tut.by Posts: 138 | From: Belarus, Western Europe | Registered: Apr 2004
posted
Hi Philip! Because nobody don’t ask me :-) I don’t like to talk alone. Moreover, I’m busy with the developing of my new tool called Jungle’s Brain Scanner. The first version will be available soon.
Posts: 138 | From: Belarus, Western Europe | Registered: Apr 2004
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OK, let be correct in definitions! As for the AMD64 Platform Nomenclature Guideline there’s no any FSB. The AMD64 platform includes definitions of HyperTransport clock and HyperTransport Link only. The first always equals to 200MHz (by default, of course), the second defines the effective speed of the link and is depended on link multiplier. Now as for your question, yes, I have already known how to change a link speed without system restart. Frankly speaking, I found the way this evening. As you remember I couldn’t generate LDTSTOP_L signal by software. Besides, my discovery may help to change a link width IN/OUT. I with Diapolo are going to realize my discovery on practice.
-------------------- PhenomII550BE+@3.6GHz/TA780G M2+/2x1GB KVR DDR2-800/WD500GB/RaidMAX case 500W/WS2003SP2 http://cbid.at.tut.by Posts: 138 | From: Belarus, Western Europe | Registered: Apr 2004
posted
ok I am new here, just played a little with cbid
or looked through the menus turned on speedfan and there i discovered that my cpufan did not spin, the themp reach 62 degrees and suddently it started..
Is that cbid that controlled that or?
just found out that when i start EVEREST my fan stops and then starts again when temp reaches 62 degrees.
my cpu is an 3500 whinchester on msi rs480m2 board
Posts: 3 | From: Denmark | Registered: Mar 2005